For a full version of my CV in pdf format click here.

Nikolaos Vassiliadis

Education

Research Interests

1. Reconfigurable Computing
  1.1. Reconfigurable Instruction Set Extensions
  1.2. Micro-architecture of interfaces to couple of Processors with Reconfigurable Hardware
  1.3. Design of Coarse-grain Reconfigurable Hardware
  1.4. FPGAs
2. Computer Architecture
  2.1. Methodologies for design of application specific processors
  2.2. Instruction Set Architectures
  2.3. Processor micro-architecture
3. Hardware-Software Co-Design
4. Architecture/Hardware Description Languages
5. VLSI

Work Experience

2005 Participation to the research project “Wireless Services in System-on-Silicon”, funded by the Greek Ministry of Industry, Energy and Technology” PEPER-GGET. Work description: Review and evaluate techniques to design low-power software for wireless telecommunication networks.

2004 Participation to the EU funded research project IST 2000-30093: “Energy-Aware SYstem-on-chip design of the HIPERLAN/2 standard (EASY)”. (link) Work description: Preparation of presentation material.

2002-2004 Participation to the EU funded research project IST-2001-34379: “Architectures and methodologies for dynamic reconfigurable logic”. (link) Work description: Primary researcher of the AUTH team which was responsible for the implementation of a low power Field Programmable Gate Area (FPGA). Primary designer of the FPGA’s architecture. Contribute in the circuit and layout design of the chip. Contribute in the development of the software tools for the configuration of the FPGA.

Publications

A. Publications in International Journals

1.  N. Vassiliadis, G. Theodoridis, S. Nikolaidis, “Exploring Opportunities to Improve the Performance of a Reconfigurable Instruction Set Processor,” International Journal of Electronics, Accepted for publication 2007.

2.  N. Vassiliadis, N. Kavvadias, G. Theodoridis, S. Nikolaidis, “A RISC architecture extended by an efficient tightly coupled reconfigurable unit,” International Journal of Electronics, Volume 93, Number 6 / June 2006, p. 421 - 438.

3.  N. Vassiliadis, A. Chormoviti, N. Kavvadias, S. Nikolaidis, “The effect of data-reuse transformations on multimedia applications for application specific processors,” International Scientific Journal of Computing, vol.4, issue 3, 2005, p.102-109.

4.  K. Siozios, G. Koutroumpezis, K. Tatas, N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas, D. Soudris, S. Nikolaidis, S. Siskos “A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications”, in IEICE Transactions on Information and Systems "Special Issue on Recent Advances in Circuits and Systems", vol. E88-D, No. 7 July 2005, pp. 1369-1380.

5.  V. Kalenteridis, H. Pournara, K. Siozos, K. Tatas, N. Vassiliadis, I. Pappas, G. Koutroumpezis, S. Nikolaidis, S. Siskos, D.J. Soudris and A. Thanailakis, “A complete platform and toolset for system implementation on fine-grain reconfigurable hardware”, Microprocessors and Microsystems, Volume 29, Issue 6, 11 August 2005, Pages 247-259.

B. Publications in International Conferences

1.  N. Vassiliadis, G. Theodoridis, S. Nikolaidis “The ARISE Reconfigurable Instruction Set Extensions Framework” International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS) 2007, accepted for publication.

2.  N. Vassiliadis, G. Theodoridis, S. Nikolaidis “Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support”, accepted for publication in Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC2006), DELFT, The Netherlands, March 1-3, 2006.

3.  N. Vassiliadis, G. Theodoridis, S. Nikolaidis “An Automated Development Framework for a RISC Processor with Reconfigurable Instruction Set Extensions”, accepted for publication in Proceedings of the 13^th Reconfigurable Architectures Workshop (RAW), Rhodes Island, Greece, April 25 – 26, 2006, pp. 212.

4.  K. Siozios, G. Koutroumpezis K. Tatas, N. Vassiliadis, H. Pournara, I. Pappas, D. J. Soudris, S. Nikolaidis, S. Siskos, V. Kalenteridis, A. Thanailakis “AMDREL: Project in retrospective”, IFIP Int. Conf. in Very Large Integration VLSI-SOC, October 17-19, 2005, Perth, Australia.

5.  N. Vassiliadis, A. Chormoviti, N. Kavvadias, S. Nikolaidis “The Effect of Data-Reuse Transformations on Multimedia Applications for Application Specific Processors”, Accepted for publication in Proceedings of the IEEE Third International Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS'2005), SOFIA, BULGARIA, September 5-7, 2005.

6.  A. Chormoviti, N. Vassiliadis, G. Theodoridis, and S. Nikolaidis “Enhancing Embedded Processors with Specific Instruction Set Extensions for Network Applications”, Accepted for publication in Proceedings of the IEEE Third International Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS'2005), SOFIA, BULGARIA, September 5-7, 2005.

7.  N. Vassiliadis, N. Kavvadias, G. Theodoridis, and S. Nikolaidis “A RISC architecture extended by an efficient tightly coupled reconfigurable unit”, in Proceedings Of The International Workshop On Applied Reconfigurable Computing (ARC), pp. 41-49, February 2005, Algarve, Portugal.

8.  N. Vassiliadis, A. Chormoviti, N. Kavvadias, S. Nikolaidis “The effect of data-reuse transformations on multimedia applications for different processing platforms”, in Proceedings of the 13th International Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS), pp. 593-602, September 2004, Santorini, Greece.

9.  D. Soudris, S.Nikolaidis, S.Siskos, K.Tatas, K.Siozios, G.Koutroumpezis, N.Vassiliadis, V.Kalenteridis, H.Pournara, I.Pappas, and A.Thanailakis, “AMDREL: A novel low-energy FPGA architecture and supporting cad tool design flow”, ASP-DAC 2005 (Asia and South Pacific Design Automation Conference 2005), January 18 - 21, 2005, Shanghai, China.

10.  I.Pappas, V.Kalenteridis, N.Vassiliadis, H.Pournara, K.Siozios, G.Koutroumpezis, K.Tatas, S.Nikolaidis, S.Siskos, D.J.Soudris, and A.Thanailakis, “Fine-Grain Reconfigurable Platform: FPGA Hardware Design and Software Toolset Development”, Journal of Physics: Conference Series, Volume 10, 2005, Pages 352-357, 2^nd Conference on Microelectronics, Microsystems and Nanotechnology MMN 2004, November 14-17, 2004, Athens, Greece.

11.  H.Pournara, V.Kalenteridis, I.Pappas, N.Vassiliadis, S.Nikolaidis, S.Siskos, and D.J.Soudris, “Energy Efficient Fine-Grain Reconfigurable Hardware”, 12^th IEEE Mediterranean Electrotechnical Conference MELECON 2004, May 12 - 15, 2004 Dubrovnik, Croatia.

12. N. Vassiliadis, S. Nikolaidis, S. Siskos and D. Soudris “The Effect of the Interconnection Architecture on the FPGA Performance and Energy Consumption”, in Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (MELECON) 2004.

13. V. Kalenteridis, H. Pournara, K. Siozios, K. Tatas, I. Pappas, N. Vassiliadis, G. Koutroumpezis, S. Nikolaidis, S.Siskos, D. J. Soudris and A. Thanailakis “An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development”, in Proceedings of the 11th Reconfigurable Architectures Workshop (RAW) April 26-27 2003, Santa Fe, New Mexico, USA.

14. K. Tatas, K. Siozios, N. Vasiliadis, D. J. Soudris, S. Nikolaidis, S. Siskos, and A. Thanailakis “FPGA Architecture Design and Toolset for Logic Implementation”, in Proceedings of the 13th International Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS), pp. 607-616, September 2003, Turin, Italy.

C. Technical Reports

1. AMDREL (IST-2001-34379)-Deliverable D14: “Power Efficient Configurable Logic Block”.

2. AMDREL (IST-2001-34379)-Deliverable D26: “Structure and Organization of Fine Grain Reconfigurable Hardware”.

3. PEPER 100 Deliverable: “Development of techniques for the design of low power software”.

D. Book Chapters

1.  D. Soudris, K. Tatas, K. Siozios, G. Koutroumpezis, S. Nikolaidis, S. Siskos, N. Vasiliadis, V. Kalenteridis, H. Pournara and I. Pappas. Chapter: “AMDREL: A Novel Low-Energy F PGA Architecture and Supporting CAD Tool Design”. Book: “Fine and Coarse-Grain Reconfigurable Computing: Architectures, Processors, Case Studies”, Kluwer Academic Publishers. (To appear in winter 2005/2006).

Honors and Awards

-Honourable mention for design contest entry for the design "AMDREL: A novel low-energy FPGA architecture and supporting CAD tool design flow" VLSI Design Contest, January 2005, Taj Bengal, Kolkata, India.

-Research funded by PENED 2003 programme of the General Secretariat for Research and Technology of Greece and the European Union.

Service

-Teaching of the lab course: “Digital Systems Laboratory-Digital design and implementation on CPLD-FPGA” for the Program of Post Graduate Studies of Electronics Physics (Electronics division), Department of Physics, Aristotle University of Thessaloniki.

Reviewer for:

- International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS VII).

- International Workshop on Applied Reconfigurable Computing (ARC2007).

- Journal of Systems and Software.

- IEEE Mediterranean Electrotechnical Conference (MELECON2006).

- Design, Automation and Test in Europe (DATE'07).