Curriculum vitae - Nikolaos Kavvadias

Nikolaos Kavvadias received the B.Sc. degree in physics and M.Sc. in electronics engineering from the Aristotle University of Thessaloniki, Greece in 1999 and 2002, respectively. Currently he is in pursuit of his Ph.D. degree in computer engineering at the same university. His current research interests include hardware and architecture description languages, application-specific processor design methodologies, and energy consumption modeling for embedded processors.






    Journal publications

  1. N. Kavvadias, P. Neofotistos, S. Nikolaidis, K. Kosmatopoulos and T. Laopoulos, "Measurements Analysis of the Software-Related Power Consumption in Microprocessors," IEEE Transactions on Instrumentation and Measurement, Vol. 53, No. 4, Aug. 2004, pp. 1106-1112. (bibtex)


  2. S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, and S. Blionas, "Instruction Level Energy Modeling for Pipelined Processors," Journal of Embedded Computing, Vol. 1, No. 3, pp. 117-124.


  3. N. Kavvadias and S. Nikolaidis, "Zero-overhead loop controller for implementing multimedia algorithms," IEE Proceedings - Computers & Digital Techniques, Vol. 152, No. 4, Jul. 2005, pp. 517-526. (bibtex)


  4. N.D. Vassiliadis, N. Kavvadias, G. Theodoridis, and S. Nikolaidis, "A RISC architecture extended by an efficient tightly coupled reconfigurable unit," to be published in the International Journal of Electronics.


  5. N. Vassiliadis, A. Chormoviti, N. Kavvadias and S. Nikolaidis, "The effect of data-reuse transformations on multimedia applications for application specific processors," International Scientific Journal of Computing, Vol. 4, No. 3, 2005, pp. 102-109.


  6. N. Kavvadias, V. Giannakopoulou and S. Nikolaidis, "Development of a customized processor architecture for accelerating genetic algorithms," accepted for publication in the Journal of Microprocessors and Microsystems. (Elsevier full-text link.)



    Conference proceedings

  1. N. Kavvadias, A. Zanikopoulos, Ch. Voliotidis, S. Kougia, A. Chatzigeorgiou, N. Zervas, S. Nikolaidis, "Power exploration of parallel embedded architectures implementing data-reuse transformations," Proc. of the 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS'01), Vol. I, pp. 781-784, September 2001. (bibtex)


  2. N. Kavvadias, A. Chatzigeorgiou, N. Zervas, S. Nikolaidis, "Memory hierarchy exploration for low power architectures in embedded multimedia applications", Proc. of IEEE 2001 International Conference on Image Processing (ICIP'01), October 2001. (presentation, bibtex)


  3. N. Kavvadias and S. Nikolaidis, "Parametric Architecture for Implementing Multimedia Algorithms", Proc. of the 9th International Conference on Digital Signal Processing (DSP2002), Santorini, Greece, July 2002. (presentation, bibtex)


  4. S. Nikolaidis, N. Kavvadias, P. Neofotistos, K. Kosmatopoulos, T. Laopoulos, L. Bisdounis, "Instrumentation set-up for Instruction level power modeling", in Proc. of 12th International Workshop on Power Analysis and Timing Modeling, Optimization and Simulation (PATMOS 2002), September 2002. (bibtex)


  5. N. Kavvadias, P. Neofotistos, S. Nikolaidis, K. Kosmatopoulos and Th. Laopoulos, "Measurements Analysis of the Software-Related Power Consumption in Microprocessors", in Proc. of the IEEE Instrumentation and Measurement Technology Conference, Vail, CO, USA, May 2003. (bibtex)


  6. S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas, "Instruction Level Modeling for Pipelined Processors", Proceedings of the 13th International Workshop on Power Analysis and Timing Modeling, Optimization and Simulation (PATMOS 2003), September 2003. (bibtex)


  7. N. Kavvadias and S. Nikolaidis, "Tradeoffs in the Design Space Exploration of Application-Specific Processors," in Proceedings of the IFIP WG 10.5 Conference on Very Large Integration of System-on-Chip (VLSI-SoC 2003), pp. 233-238, December 1-3, 2003, Darmstadt, Germany. (bibtex)


  8. N. Vassiliadis, A. Chormoviti, N. Kavvadias, and S. Nikolaidis, "The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms," Proc. of the 14th Intl. Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 593-602, September 15-17, 2004, Santorini, Greece. (bibtex)


  9. N. Kavvadias and S. Nikolaidis, "Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors," Proc. of the 14th Intl. Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 633-642, September 15-17, 2004, Santorini, Greece. (bibtex)


  10. N. Kavvadias and S. Nikolaidis, "Hardware support for arbitrarily complex loop structures in embedded applications," in Proceedings of the Design, Automation and Test in Europe Conference (DATE'05), pp. 1060-1061, March 7-11, 2005, Munich, Germany. (bibtex)


  11. N.D. Vassiliadis, N. Kavvadias, G. Theodoridis, and S. Nikolaidis, "A RISC architecture extended by an efficient tightly coupled reconfigurable unit," in Proceedings of the 1st International Workshop on Applied Reconfigurable Computing 2005 (ARC 2005), pp. 41-49, February 22-23, 2005, Algarve, Portugal. (bibtex)


  12. N. Kavvadias and S. Nikolaidis, "Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding," in Proceedings of the IEEE 16th International Conference on Application-specific Systems, Architectures and Processors, pp. 140-145, July 2005, Samos, Greece. (bibtex)


  13. N. Vassiliadis, A. Chormoviti, N. Kavvadias, and S. Nikolaidis, "The Effect of Data-Reuse Transformations on Multimedia Applications for Application Specific Processors," in Proceedings of the IEEE Third International Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS'2005), September 5-7, 2005, Sofia, Bulgaria.


  14. N. Kavvadias and S. Nikolaidis, "A portable specification of zero-overhead looping control hardware applied to embedded processors," pp. 1599-1602, in Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, May 21-24, 2006, Kos, Greece.


  15. N. Kavvadias and S. Nikolaidis, "A flexible instruction generation framework for extending embedded processors," in Proceedings of the 13th IEEE Mediterranean Electrotechnical Conference (MELECON 2006), pp. 125-128, May 16-19, 2006, Benalmadena (Malaga), Spain.








  1. A data-dependence graph construction pass for MachSUIF called 'bbpart'). 'bbpart' is an analysis pass built to be used with the SUIF2/MachSUIF2 compiler infrastructure. This pass generates a textual representation for the data dependence graphs of the basic blocks found in all the procedures of a given ANSI C source file. An older version that generates a visual representation in the VCG (Visualization and Compiler Graph) format for each DDG can be found here.


  2. Instruction-accurate ArchC model for the (integer ISA) DLX processor (alpha version): (model)

  3. [UPDATED: 10-October-2006]

  4. An implementation of a hardware looping unit (HWLU) in VHDL: (link)


  5. SUIFvm instruction set support for the CDIF (Connected Dataflow Idiom Finder) instruction generation tool: (patch)
    [FIXED: 30-March-2006]


  6. A patch for the OLIVE code generator-generator tool, currently only available as part of the SPAM research compiler, which is built on top of SUIF 1. The patch has been tested on Linux Redhat 9.0 with its pre-installed gcc-3.3.2. (patch)
    [FIXED: 29-August-2006]


  7. A patch applying modifications to archc-2.0beta2 (the latest ArchC distribution as of 07-July-2006) so that it can compile with a gcc-2.x-based compiler. It has been (not thoroughly) tested on a Linux Redhat 7.3 with its native gcc-2.96: (patch)








  1. 'tcfggen' is an analysis pass built to be used with the SUIF2/MachSUIF2 compiler infrastructure. 'tcfggen' performs (natural) loop analysis in order to map the control flow of a given optimization unit (i.e. a procedure in the input program) to its task control flow graph (TCFG). It is also used to pass the static information for the loops in the given procedure to the subsequent stage(s) in the form of pseudo-instructions. These pseudo-instructions pass information regarding:
    • a) the task transitions,

    • b) the points for task entry and task exit

    • c) the loop parameters (loop bounds and stride) and the basic induction register

    • d) which instructions should be removed for ZOLC execution


    This pass works for the SUIFrm instruction set and has been tested with MachSUIF 2.02.07.15.


  2. 'zolcgen' is a transformation pass operating on SUIFrm assembly files, utilizing the SALTO (System for Assembly Language Transformation and Optimization) API. This pass produces the actual ZOLC initialization code that has to be inserted in a preceding basic block to the loop nest to update the ZOLC storage resources and is typically the first basic block of the targeted procedure. This pass works for the SUIFrm instruction set and has been created for a modified SALTO distribution based on version 1.4.1beta3.


  3. SUIFrm (SUIF real machine) backend for Machine-SUIF 2.02.07.15 (coming soon!)


  4. SUIFrm instruction-based simulation model (with ZOLC extensions) written for ArchC 2.0beta2 (coming soon!)


  5. SUIFrm machine description for SALTO (coming soon!)


  6. Kernel benchmarks for evaluating the ZOLC optimizations (tests)